1. Technical Field
The present invention relates generally to integrated circuits, and more particularly, to power consumption reduction by stage in an integrated circuit.
2. Related Art
The trend towards portable integrated circuit (IC) applications, requires IC designs with increased performance and reduced power consumption. Accordingly, the challenge continues to be to design ICs with reduced power consumption by operating at the minimum performance level required by the active software and/or application.
One current approach to power savings is by providing dynamic voltage control per stage in an IC path, i.e. pipeline. One example of this approach is disclosed in xe2x80x9cDesign Issues for Dynamic Voltage Scaling,xe2x80x9d by Burd and Broderson, ISLEP, 2000, Rapallo, Italy. In this example, the clock frequency and supply voltage are varied on demand. In particular, in this example, the operating system is knowledgeable of the current logic functional unit execution performance requirements, and controls the clock frequency by writing to a register in the system control states. A dynamic voltage scaling feedback loop architecture then converts a desired operating frequency into the operating voltage (Vdd). Unfortunately, the above example requires level shifting, which impacts performance.
Another example of this approach is disclosed in xe2x80x9cXScale (StrongARM-2) Muscles In,xe2x80x9d Microdesign Resources, Sep. 11, 2000. In this example, a processor contains performance-monitoring hardware consisting of counters and timers to measure performance-related characteristics such as cache-stall cycles, bus latency, and idle cycles. The operating system or application code can then dynamically adjust processor performance so as to minimize power consumption. For example, the voltage delivered to the processor may be varied via off-chip voltage sources. This approach requires voltage switching off-chip and addresses power reduction only at a full execution-unit level basis.
In view of the foregoing, there is a need in the art a method and system for on-chip voltage control per stage for performance and power optimization at a finer granularity than disclosed in the related art.
An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of each stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given execution for performance and power optimization.
A first aspect of the invention is directed to an integrated circuit comprising: a plurality of paths including a critical path for a particular cycle, the critical path including a plurality of stages; and means, within the integrated circuit, for dynamically changing a voltage level of at least one stage for the particular cycle.
A second aspect of the invention is directed to a method of reducing power consumption of an integrated circuit comprising: transmitting data along one of a plurality of paths based on a particular operation to be executed, each path including a plurality of stages that operate on the data; and changing a voltage level of at least one stage.
A third aspect of the invention is directed to a system for reducing power consumption of an integrated circuit, the system comprising: means, within the integrated circuit, for determining a voltage level required for each stage on a path used for a particular cycle; and means, within the integrated circuit, for changing the voltage level of at least one stage on the path.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.